• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
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    • 专利摘要:
    The method for activating dopants in a GaN-based semiconductor comprises a first step of providing a substrate (1) comprising (i) a layer of GaN-based semiconductor material (1b) comprising doping impurities (2), (ii) a protective block (3) free of silicon-based compound, in contact with the layer of semiconductor material (1b), (iii) a cover layer (4) based on silicon covering the protection block (3). The method comprises a second heat treatment step at a temperature above 900 ° C so as to activate the electrical doping impurities (2) in the layer of semiconductor material (1b).
    公开号:FR3026558A1
    申请号:FR1459126
    申请日:2014-09-26
    公开日:2016-04-01
    发明作者:Claire Agraffeil
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    [0001] FIELD OF THE INVENTION The invention relates to a method for activating dopants in a semiconductor layer. State of the art Ion implantation is commonly used to dope semiconductors. The ions used for doping are generally produced from a gaseous or solid source and impact the semiconductor after being accelerated, for example, at an energy of between 10 and 500 keV. Once the implantation is complete, the doped semiconductor undergoes a heat treatment intended on the one hand to restore the crystalline quality of the semiconductor, and on the other hand to activate the dopants, that is to say to enable them to substitute for certain atoms of the crystalline semiconductor network. The applied thermal budget also causes their diffusion in the semiconductor.
    [0002] For example, to obtain a high activation rate of Si + ions (n-doping) or Mg + ions (p-doping) in a GaN semiconductor layer, a solution can be to perform a heat treatment of the material. without covering it with a protective layer. The heat treatment may, for example, be carried out at a temperature greater than 1000 ° C., at a pressure greater than 15 kbar, and under a controlled nitrogen atmosphere. However, performing annealing at such a high pressure is only possible if a suitable device is available which limits the interest of such a method. If the heat treatment is not carried out at high pressure, the surface of the semiconductor can be altered. For example, GaN is a semiconductor whose surface can be degraded when the annealing temperature is above 850 ° C and when the annealing is carried out at atmospheric pressure. Cracks or holes may appear on the surface of the semiconductor material.
    [0003] To prevent the deterioration of the semiconductors, a protective layer ("cap-layer" in English) can be deposited above the semiconductor before or after the ion implantation, and before carrying out the heat treatment. The protective layer anneals the semiconductor at a higher temperature than it could withstand without applying a high pressure such as 15kbar. The doped semiconductor then has fewer defects. The document "Si implanted reactivation in GaN grown on sapphire using AIN and oxide cap layers" (F. Cayrel et al., Nuclear Instruments and Methods in Physics Research B, 272 (2012) 137-140) compares the effectiveness of a protection layer of 5iO 2 and a protective layer of AlN deposited on a semiconductor layer of GaN. Thanks to one or other of the protective layers, anneals lasting from 30 seconds to 8 hours at temperatures of between 1000 and 1150 ° C. are possible. The surface roughness of the GaN layer is lower when the protective layer is a 5iO 2 layer. On the other hand, the specific contact resistance is better when the protective layer is an AlN layer, which means that the electrical activation of the dopants is higher with the AlN layer than with the SiO 2 layer.
    [0004] The document "Activation of ion implanted Si in GaN using a dual AIN annealing cap" (CE Nager et al., J Appl Phys 105, 033713, (2009)) shows the interest of two layers of AIN superimposed for the n-type doping of a GaN semiconductor. Here, the stack comprises: a first layer with a thickness of the order of 80 nm, deposited by a metalorganic chemical vapor vapor deposition ("MOCVD"), at the same temperature as the growth temperature of the semiconductor, and acting as an adhesion layer since the thermal expansion coefficients of GaN and AlN are of the same order of magnitude; a second layer of AlN having a thickness of about 1 μm deposited by cathodic sputtering above the first layer, with the aim of reinforcing the protection conferred by the first layer. With these two layers, it is possible to anneal the semiconductor at temperatures up to 1250 ° C for 30 minutes. This makes it possible to obtain an electrical activation rate of the atoms of the order of 70%, while limiting the degradation of the surface of the GaN semiconductor. OBJECT OF THE INVENTION It is noted that there is a need to provide a method of activating dopants in a GaN-based semiconductor which makes it possible to obtain a high activation rate while avoiding a deterioration of the surface of the surface. This problem is solved by means of a method which comprises the following steps: providing a substrate comprising: a layer of GaN-based semiconductor material provided with electrical doping impurities, a protection block devoid of a silicon-based compound, in contact with the semiconductor material layer, a silicon-based covering layer covering the protection block, carrying out a heat treatment at a temperature greater than 850 ° C so as to activate the electrical doping impurities in the layer of semiconductor material. According to one aspect of the invention, the dopant activation method can be implemented for n-type doping. The protection block can then be an AlGaN layer with a thickness of between 1 and 40 nm, preferably between 5 and 20 nm. The AlGaN layer may comprise up to 50% of Ga, advantageously up to 20% of Ga, and preferably less than 5% of Ga. According to one alternative, the AlGaN layer may be completely devoid of Ga. alternatively, the dopant activation method can be implemented for p-type doping. The protection block may then comprise a layer of Mg or MgO of thickness between 1 and 30 nm, preferably between 1 and 15 nm, ideally between 4 and 5 nm. It may further comprise an AlGaN layer positioned between the semiconductor material layer and the Mg or MgO layer, the AlGaN layer having a thickness of between 1 and 40 nm, preferably between 5 and 20 nm. . The AlGaN layer may then comprise up to 50% of Ga, advantageously up to 20% of Ga, and preferably less than 5% of Ga. According to one alternative, the AlGaN layer may be completely devoid of Ga. According to a particular embodiment, the protection block may also comprise an additional layer of AlN or AlGaN, with a thickness of between 1 and 40 nm, preferably between 5 and 20 nm, positioned between the Mg or MgO layer. and the cover layer. According to one aspect of the invention, the deposition of the covering layer can be performed at a temperature below 850 ° C, preferably between 700 and 800 ° C. The material of the cover layer may be selected from silicon, silicon oxide, or silicon nitride. The thickness of the cover layer may be between 5 and 500 nm, preferably between 50 and 150 nm, and ideally equal to 100 nm.
    [0005] Moreover, the implantation of the doping ions can be carried out at a temperature of between 15 ° C. and 700 ° C.: before the deposition of the protection block, or after the deposition of the protective block and before the deposition of the layer. cover, or - after the deposit of the covering layer. As regards the heat treatment, this may be carried out under an atmosphere comprising a gas chosen, for example, from N 2, NF 3, NH 3, Ar He, or mixtures of N 2 / H 2 or Ar / H 2. It may comprise at least one annealing carried out at a temperature greater than 1000 ° C. The heat treatment step can also be carried out at a pressure of between 1 bar and 15 kbar, preferably between 1 bar and 1kbar, and preferably between 1 and 10 bar, and ideally at 1 bar.
    [0006] Finally, the thickness of the layer of semiconductor material may be between 5 nm and 10 μm, preferably 500 nm and 10 μm, advantageously equal to 1 μm.
    [0007] BRIEF DESCRIPTION OF THE DRAWINGS Other advantages and features will emerge more clearly from the following description of particular embodiments of the invention given by way of non-limiting example and represented in the accompanying drawings, in which: FIG. a substrate having a layer of semiconductor material; - Figure 2 illustrates an implantation phase of electrical doping impurities; - Figures 3 to 7 illustrate four possible configurations of a substrate covered with a protective block; FIG. 8 shows a substrate covered with a protective block and a cover layer; FIG. 9 illustrates the heat treatment stage intended to activate the electrical doping impurities; FIGS. 10 and 11 illustrate steps of FIG. etching for removing the cover layer and the protective block from the substrate, - Figure 12 shows the substrate provided with a layer of semi-conductive material with activated electrical dopant impurities. DETAILED DESCRIPTION According to one embodiment of the dopant activation method shown in FIGS. 1 to 12, provision must first be made of a substrate 1 advantageously comprising a support, for example made of silicon, sapphire, Al 2 O 3, SiC. , and a layer of GaN-based semiconductor material 1b (see FIG. 1). Alternatively, the substrate 1 may be solid GaN.
    [0008] When the substrate 1 is a solid block of GaN, it is possible to cover the rear face with protective layers that are advantageously identical to those deposited on the substrate 1 on the front face, and which will be described below. The front face of the substrate 1 is defined here as the face impacted by the doping impurities beam, and the rear face as the opposite face to the front face. The embodiment of the substrate 1 may comprise a first cleaning step of the support 1a, for example an RCA-type cleaning if the support is made of silicon.
    [0009] The layer of semiconductor material 1b is then manufactured by epitaxial growth directly on the support 1a. The material of the support la must be carefully selected to have mesh parameters similar to those of the layer of semiconductor material lb so that the latter increases in a coherent manner. To improve the quality of the semiconductor material layer 1b, an AlGaN-based intermediate layer may optionally be deposited on the support 1a before the epitaxial growth of the layer 1b (embodiment not shown).
    [0010] When the semiconductor material layer 1b has been completed, the latter may have a thickness of between 5 nm and 10 pm, advantageously between 5 nm and 10 pm, preferably 500 nm and 10 pm, ideally equal to 1 pm.
    [0011] The substrate 1 is intended to be annealed at an elevated temperature, for example greater than 850 ° C. in order to activate dopant species 2 after implantation. However, beyond a temperature of the order of 850 ° C., the layer of GaN-based semiconductor material 1b is highly degraded. Protective layers are therefore used in order to carry out the heat treatment of the substrate 1 at a high temperature while strongly limiting the degradation of the surface of the semiconductor layer 1b. For this purpose, a protection block 3 devoid of any silicon-based compound is deposited on the substrate 1. Its nature depends on the type of doping desired for the semiconductor layer 1b.
    [0012] When the desired doping of the semiconductor material layer 1b is n-type doping, the protection block 3 is preferably formed of a single layer of AlGaN 3a (see FIG. 3). One of the roles of AlGaN is to allow the annealing of the semiconductor layer 1b while limiting the degradation of the surface of the material and making it the least resistive possible. AlGaN is a carefully selected material because its mesh parameters are very close to those of the gallium nitride semiconductor material, which makes it possible to increase the adhesion of the protection block 3 to the substrate 1. L AlGaN also makes it possible to produce a semiconductor material layer 1b having not only good electrical quality, but also an improved surface state and which is less resistive than in the prior art. The AlGaN layer 3a can comprise up to 50% of Ga, advantageously less than 20% of Ga and preferably less than 5% of Ga (in atomic percentages). In a particular case, the AlGaN layer may be completely devoid of Ga and therefore be an AlN layer.
    [0013] The AlGaN layer 3a may for example be deposited by MOCVD in a device identical to that used for the epitaxial growth of the layer of semiconductor material 1b. The deposition can be carried out at the nucleation temperature of the semiconductor material or at a lower temperature, of the order of 500 ° C., for example. It is advantageous to deposit the layer 1b and the layer 3a in the same equipment without the substrate being brought into contact with the air.
    [0014] Alternatively, in the case of n-type doping, the protection block 3 may be a single layer of AlN 3a. This can be done by MOCVD, Physical Vapor Deposition (PVD) or any other deposition technique in the field of microelectronics to deposit this type of layer.
    [0015] The layer 3a advantageously has a thickness of between 1 and 40 nm, more preferably between 5 and 20 nm, and ideally equal to 10 nm. This thickness is sufficient to create an effective barrier to prevent the evaporation of nitrogen molecules from the semiconductor material layer 1b during annealing. A thickness of 10 nm is sufficient to prevent degradation of the layer 3a during the heat treatment, up to cracks depriving the semiconductor layer protective barrier. This thickness is also sufficiently low to be eliminated without difficulty at the end of the doping process.
    [0016] In the case where a p-type doping is desired, a protection block 3 comprising an AlGaN layer and a Mg or MgO layer may be deposited on the substrate 1. According to the embodiments, the Mg or MgO layer can separate the AlGaN layer and the layer of semiconductor material 1b. It is also possible to provide that the Mg or MgO layer is separated from the semiconductor material layer 1b by the AlGaN layer. According to a first embodiment illustrated in FIG. 4, the protection block 3 comprises a layer of AlGaN or AlN 3a in contact with the layer of semiconductor material 1b, and a layer of Mg or MgO 3b in contact with layer 3a. The Mg or MgO layer acts as a reservoir of Mg atoms which constitute p-type doping impurities that can diffuse through the AlGaN layer 3a to the layer of semiconductor material 1b. The layer based on AlGaN also prevents the diffusion to the semiconductor material layer 1b of species belonging to other layers that can be deposited above the layer 3b.
    [0017] The deposition of the AlGaN layer 3a is advantageously carried out according to a process similar to that just described in connection with n-doping. The thickness of the AlGaN layer 3a is between 1 and 40 nm, preferably between 5 and 20 nm and ideally equal to 10 nm. This thickness range makes it possible to have a layer 3a sufficiently weak to allow the diffusion of the Mg atoms in the direction of the layer 1b and of sufficient thickness to ensure the barrier function for the other undesired species.
    [0018] The Mg or MgO 3b layer advantageously has a thickness of between 1 and 30 nm, preferably between 1 and 15 nm, and ideally between 4 and 5 nm. At equal thickness, the inventors have however observed that the use of a layer of Mg instead of a layer of MgO makes it possible to produce a layer of semiconductor material of better quality (higher doping, better electrical quality, lower resistivity, etc.).
    [0019] The Mg or MgO 3b layer is deposited on the first layer of AlGaN or AIN 3a by an ion gun ("Ion Beam Deposition" or IBD in English), by Physical Vapor Deposition ("Physical Vapor Deposition"). or "PVD" in English), or any other deposition technique known to those skilled in the art for depositing this type of material The deposition may for example be carried out at ambient temperature and at atmospheric pressure. The combination of a layer of AlGaN 3a and a layer of Mg or MgO 3b prevents, during the heat treatment, the formation of a dopant concentration well in the layer of semiconductor material 1b and an accumulation dopants on its surface. The distribution of the dopants as a function of the depth in the semiconductor material 1b is more homogeneous than with the techniques of the prior art.
    [0020] In an alternative embodiment of the protection block 3, an additional layer of AIN or AlGaN 3c may be deposited on the Mg or MgO 3b layer (see FIG. If the layer 3c is made of AlGaN, it may comprise up to 50% of Ga, advantageously less than 20% of Ga and preferably less than 5% of Ga (in atomic percentages). This layer 3c may have a thickness of between 1 and 40 nm, preferably between 5 and 20 nm and ideally equal to 10 nm. This thickness is sufficient for the layer 3c to play its role of diffusion barrier against species from layers deposited above the layer 3c. If the layers 3a and 3c are used, the sum of the thicknesses of the layers 3a and 3c may advantageously be in the range 10-20 nm to ensure the barrier function. It is also possible to provide that the sum of the thicknesses of the layers 3a and 3c and the layer of Mg or MgO is in the range 14-25nm to provide the barrier function. The growth of the AlN 3c layer may for example be carried out by MOCVD, by PVD, or by any deposition technique in the field of microelectronics for depositing this type of material. The temperature at which the deposit is made is less than or equal to the nucleation temperature of the semiconductor material.
    [0021] The AIN or AlGaN layer 3c also makes it possible, in combination with the AlGaN layer 3a, to sandwich the layer of Mg or MgO 3b, and to ensure the good temperature resistance of the protection block 3 during the 2. This particular stack makes it possible to have a protection block containing a layer of Mg or MgO and which has a coefficient of thermal expansion close to that of the layer 1b, which reduces the problems of adhesion. . By way of example, in a particularly advantageous embodiment of the protection block 3, it comprises a layer of AlGaN 3a, a layer of Mg or MgO 3b and a layer of AlN 3c in which the sum of the thicknesses layers 3a and 3c is about 10 nm. The inventors have indeed observed that such a thickness of AlGaN and / or AlN prevents the formation of a concentration well of Mg in the layer of semiconductor material 1b, as well as an accumulation of impurities. Mg doping on its surface. According to an alternative embodiment that can be used for a p-type doping, the protection block 3 may comprise a layer of Mg or MgO 3b deposited directly on the semiconductor material layer 1b, and a layer of AlN or d AlGaN 3c deposited on layer 3b (see FIG.
    [0022] The techniques used to deposit the layer 3b are similar to those mentioned above, in particular by IBD or PVD. This embodiment has the advantage of being simpler to implement with respect to the establishment of a protective block having three layers. It should be borne in mind, however, that the removal of the layer 3b directly deposited on the layer of semiconductor material 1b is more difficult than the removal of a layer of AlN or AlGaN.
    [0023] In this embodiment, the layer 3b in Mg or MgO advantageously has a thickness of between 1 and 30 nm, preferably between 1 and 15 nm, and ideally between 4 and 5 nm. The layer 3c in AlN or AlGaN may have a thickness of between 1 and 40 nm, preferably between 20 nm and ideally equal to 10 nm.
    [0024] According to a fourth embodiment of the protection block 3 used for doping p of the semiconductor material layer 1b, the protection block may contain a single layer of Mg or MgO 3b (see FIG. In this case, it may be advantageous to deposit a layer 3b having a thickness greater than 10 nm so that the protection block 3 can properly play its role of protective barrier during the heat treatment. Whether the doping performed is of the n-type or the p-type, a silicon-based cover layer 4 is deposited above the protection block 3. This step is illustrated in FIG. 8. The cover layer 4 may be made of silicon amorphous, in silicon oxide, or stoichiometric silicon nitride or not and noted SixNy. The layer 4 can advantageously be made in 5i02, because this material is very resistant during temperature changes.
    [0025] When the method is used to activate n-type dopants, it is not necessary for the protection block 3 to be provided with a layer of Mg or MgO. In this case, Si atoms can diffuse through the protection block 3 towards the semiconductor material layer 1b, which reinforces the n-type doping. The deposition of the cover layer 4 can be carried out at a temperature below 850 ° C, and preferably between 700 and 800 ° C by LPCVD. Depending on the nature of the material of the layer 4, it is possible to perform a plasma-enhanced chemical vapor deposition ("Plasma Enhanced Chemical Vapor Deposition" or "PECVD" in English) in a temperature range advantageously between 200 ° C. and 600 ° C. The deposit made by LPCVD is, however, preferred for the quality of the layer obtained. It is also possible to use any other deposition technique in the field of microelectronics for depositing this type of layer. In the case where the deposition of the cover layer 4 is carried out by LPCVD, the growth rate of the material may advantageously be between 2.5 and 3.5 nm / min in a temperature range of between 700 and 800 ° C. . This range of value has the advantage of allowing a better crystalline growth of the cover layer 4, and therefore a better temperature resistance.
    [0026] Once the deposition is complete, the cover layer 4 may advantageously have a thickness of between 5 and 500 nm, preferably between 50 and 150 nm and ideally equal to 100 nm. The cover layer 4 may be thicker than the protective block 3 so as to allow a good temperature resistance of the assembly, and therefore to increase the temperature of the heat treatments applied for the activation of the dopants.
    [0027] To improve the adhesion of the cover layer 4 to the protection block 3, a cleaning of the surface of the protection block 3 can be performed prior to the step of depositing the cover layer 4. The cleaning can be carried out for example by deoxidation with a solution of ammonium hydroxide NH4OH and water ratio (1: 1) at a temperature between 60 and 70 ° C. Alternatively, the cleaning of the first cover layer can be performed by any other surface preparation chemistry adapted to the material.
    [0028] The protection block 3 also makes it possible to limit the mechanical stresses between the substrate 1 and the cover layer 4, which have very different coefficients of thermal expansion. By way of illustration, gallium nitride has a coefficient of thermal expansion equal to 5.6 × 10 -6 K -1 and the cover layer 4 may have a coefficient of thermal expansion of between 0.5 × 10 -6 K -1 and 3.3 × 10 6 -6 K-1 according to its chemical composition. The coefficient of thermal expansion of the aluminum nitride protection block 3 is 4.5 × 10 -6 K -1, which corresponds to an intermediate value between that of the substrate 1 and that of the cover layer 4. The block of protection 3 thus serves as a buffer between the substrate 1 and the cover layer 4 and limits the mechanical stresses of the stack of the different layers on each other. Furthermore, the materials of the cover layer 4 have a better temperature resistance than the AIN used to make the protection block 3. The cover layer 4 thus protects the substrate 1 and the protection block 3 during the phase heat treatment device for activating the dopants implanted in the semiconductor material layer 1b. To dopate the semiconductor material layer 1b, an implantation can be performed after the deposition of the cover layer 4, or after the deposition of the protective block 3 and before the deposition of the cover layer 4. Alternatively, the semiconductor material layer 1b can be doped directly by epitaxy during the MOCVD deposition, by ion beam or by plasma immersion before the deposition of the protective layer 3. These techniques can be implemented alone or in combination.
    [0029] When the desired doping of the layer of semiconductor material is n-type, Si + ions can be implanted in the layer 1b. Alternatively, it is conceivable to implant other species (ions or neutrals) such as Be, Ge, 0 in place of the Si type impurities.
    [0030] To perform a p-type doping, Mg + ions can be implanted in the layer of semiconductor material 1b. It is also possible to provide co-implantation Mg + / P + or co-implantation Mg + / N + in the layer of semiconductor material 1b. Another option may be to implant other species (ions or neutrals) such as Ca, Zn or C. Conventionally, the implantation conditions are imposed firstly by the technical performance of the implantation equipment, and secondly by the concentration and location of the electrical doping impurities 2 that it is desired to implant in the layer of semiconductor material 1b. For example, for a Mg + ion beam with a fluence of 2.1015 atoms / cm2 and an energy of 200keV, the depth of implantation in a semiconductor layer of GaN that is not covered with a protective layer is of the order of 400 nm.
    [0031] In the context of the invention, the ion implantation can be carried out with a fluence of between 1.1014 and 1.1016 atoms / cm 2, with an energy of between 25 and 1000 keV.
    [0032] The implantation conditions also depend on the temperature conditions, that is to say on the temperature at which the substrate 1 is located.
    [0033] According to one embodiment, the implantation can be carried out at ambient temperature, or at a temperature of between 15 ° C. and 700 ° C. The implantation of the dopants 2 at a temperature greater than the ambient temperature makes it possible to limit the degradation of the crystalline mesh of the semiconductor, and to reorganize it partially before carrying out a thermal restoration treatment. In this way, the heat treatment can be carried out for a shorter time, and at a lower temperature.
    [0034] The doping of the semiconductor material layer 1b can be carried out at different stages: either directly after the deposition of the semiconductor material layer 1b, or advantageously after the deposition of the protection block 3. Another alternative can be to achieve it after the deposition of the cover layer 4.
    [0035] When the protection block 3 comprises several layers, it is possible to perform the implantation after the deposition of any of these layers, whatever it may be.
    [0036] In this case, the implantation energy of the electrical doping impurities must be adapted to pass through the layers of the protection block 3. For an identical average implantation depth, the energy of the ion beam must be greater. when the impurities are implanted through the protection block 3 only when they are directly implanted after the step of epitaxial growth of the semiconductor material layer 1 b. The fact of implanting electrical doping impurities 2 after the deposition of the protection block 3 makes it possible, for example, to avoid a channeling effect during the ion implantation step. The channeling effect can lead to a layer of semiconductor material 1b, the electrical doping impurities 2 are deeply implanted and are not distributed homogeneously. According to a third alternative embodiment, it is possible to perform the implantation after having deposited the protection block 3 and the cover layer 4. In this case, the implantation energy of the electrical doping impurities 2 in the layer in semiconductor material 2 must be even higher than in the embodiments described above so that the electrical doping impurities 2 can pass through the protection block 3 and the cover layer 4. Once the implantation step Dopant activation is performed by heat treatment (see Figure 9). The nature of the materials of the cover layer 4 makes it possible to carry out rapid annealing ("Rapid Thermal Annealing" or "RTA" and "Rapid Thermal Processing" or "RTP" in English) so that the activation rate of doping impurities 2 is high without the surface of the semiconductor layer 1b is damaged. Standard annealing ("Furnace Annealing" in English) can also be performed to allow effective diffusion of electrical doping impurities 2 in the semiconductor layer 1b. This type of heat treatment is particularly appropriate in the case of a p-type doping, since it promotes the diffusion of the Mg dopants from the layer 3b through 3a to the semiconductor material layer 1b. During the heat treatment step, it is therefore possible to perform standard annealing, rapid annealing, or a combination of different anneals depending on the result that is desired.
    [0037] By way of illustration, standard annealing at a temperature of between 850 and 1250 ° C. can be carried out for a duration ranging from a few minutes to a few hours. Fast annealing may also be performed in a temperature range of 850 to 1350 ° C for a period of time between a few seconds and a few minutes. Advantageously, the annealing (s) can be carried out under a controlled atmosphere containing a gas chosen from N2, Ar, He, or NF3, NH3, or mixtures of N2 / H2 or Ar / H2. It is better to avoid having an oxidizing atmosphere to limit the diffusion of oxygen in the semiconductor matrix. It is preferable to use an atmosphere based or consisting of N2, Ar, He, NF3. In general, the heat treatment may consist of a single standard anneal, or a single fast annealing, or any combination of rapid annealing and standard annealing, regardless of their number and order. It may advantageously comprise at least one annealing at a temperature greater than 1000 ° C. in order to obtain a high activation rate of electrical doping impurities 2.
    [0038] Compared to GaN doping methods of the prior art, the fact of associating an AlGaN-based protection block 3 and an Si-based cover layer 4 therefore makes it possible to carry out heat treatment at a higher temperature. high and for a longer time.
    [0039] Moreover, the implementation of a standard heat treatment makes it possible to achieve an optimal distribution of the electrical doping impurities 2 by diffusion of the latter in the semiconductor layer 1b. The implementation of a fast heat treatment at high temperature also makes it possible to obtain a high activation rate of electrical doping impurities 2. The protective block 3 and the cover layer 4 prevent them from damage to the surface of the semiconductor layer 1b, the degradation of its surface state, and the modification of the chemical composition of the semiconductor material by degassing nitrogen. Moreover, the heat treatment is carried out under a pressure of between 1 and 15 kbar, advantageously between 1 bar and 1 kbar, and ideally between 1 and 10 bar. When the heat treatment step is complete, the protection block and the cover layer 4 must be removed. For this, a first etching step can be successively carried out to remove the cover layer 4 (see FIG. 10), then a second etching step to remove the protection block 3 (see FIG. The removal of the silicon-based cover layer 4 may for example be carried out by wet etching using hydrofluoric acid (HF) or phosphoric acid (H3PO4). The AIN-based protection block 3 can also be removed by wet etching with phosphoric acid or KOH.
    [0040] Alternatively and advantageously, the protection block 3 can be removed by chemical mechanical planarization ("Chemical-Mechanical Planarization" or "CMP" in English). Finally, a substrate 1 is obtained comprising a semiconductor material layer 1b having n or p doping impurities, with a very good activation rate (see FIG. 12). The activation rate of the p-type dopant impurities is between 5 and 60%, and the activation rate of the n-type doping impurities is generally between 50 and 100%.
    [0041] The invention is not limited to the features just described. Those skilled in the art can, without departing from the scope of the invention, deposit the different layers of material on the substrate by any alternative technique such as PVD sputtering, MOCVD, LPCVD, PECVD, etc. Instead of performing an ion implantation in the layer of semiconductor material 1b, the skilled person can, without departing from the scope of the invention, doping the semiconductor layer by epitaxy during its deposition. Those skilled in the art may also consider performing p-doping in certain areas of the layer made of GaN-based semiconductor material, and n-doping in different areas. It can also dope the layer of semiconductor material in certain areas and not perform doping in other areas of the layer. For this purpose, a mask may be used to protect certain areas of the substrate during ion implantation. The formation of n-doped or p-doped GaN structures is particularly useful for producing high-mobility electronic transistors, Schottky diodes and optoelectronic components such as LEDs.
    权利要求:
    Claims (19)
    [0001]
    REVENDICATIONS1. A method of activating dopants in a GaN-based semiconductor comprising the following steps: - providing a substrate (1) comprising: a GaN-based semiconductor layer (1b) provided with electrical doping impurities (2), o a protective block (3) devoid of silicon-based compound, in contact with the semiconductor material layer (1b), o a silicon-based covering layer (4) covering the protection block (3), - performing a heat treatment at a temperature above 850 ° C so as to activate the electrical doping impurities (2) in the layer of semiconductor material (1b).
    [0002]
    2. Method for activating dopants according to claim 1, in which the doping is an n-type doping, and wherein the protection block (3) is an AlGaN layer (3a) having a thickness of between 1 and 40 nm, preferably between Set 20 nm, and ideally equal to 10 nm.
    [0003]
    3. dopant activation method according to claim 2, wherein the AlGaN layer (3a) comprises up to 50% of Ga, advantageously up to 20% of Ga, and preferably less than 5% of Ga.
    [0004]
    The method of activating dopants according to claim 2, wherein the AlGaN layer (3a) is completely free of Ga.
    [0005]
    5. Method for activating dopants according to claim 1, in which the doping is a p-type doping, and wherein the protection block (3) comprises a layer of Mg or MgO (3b) with a thickness of between 1 and and 30 nm, preferably between 1 and 15 nm, and ideally between 4 and 5 nm.
    [0006]
    The method of activating dopants according to claim 5, wherein the protection block (3) further comprises an AlGaN layer (3a) positioned between the layer of semiconductor material (1b) and the layer of Mg or MgO (3b), the AlGaN layer (3a) having a thickness of between 1 and 40 nm, preferably between 5 and 20 nm.
    [0007]
    7. The process for activating dopants according to claim 5, wherein the AlGaN layer (3a) comprises up to 50% Ga, advantageously up to 20% Ga, and preferably less than 5% Ga.
    [0008]
    The method of activating dopants according to claim 7, wherein the AlGaN layer (3a) is completely free of Ga.
    [0009]
    9. dopant activation method according to any one of claims 6 to 8, wherein the protective block (3) comprises an additional layer of AlGaN (3c), thickness between 1 and 40 nm, preferably between 5 and 20 nm, positioned between the Mg or MgO layer (3b) and the cover layer (4).
    [0010]
    10. dopant activation method according to any one of claims 1 to 9, wherein the deposition of the cover layer (4) is carried out at a temperature below 850 ° C, preferably between 700 and 800 ° C .
    [0011]
    11. dopant activation method according to any one of claims 1 to 10, wherein the material of the cover layer (4) is selected from silicon, silicon oxide, or silicon nitride.
    [0012]
    12. Dopant activation method according to any one of claims 1 to 11, wherein the thickness of the cover layer (4) is between 5 and 500 nm, preferably between 50 and 150 nm, and ideally equal to at 100 nm.
    [0013]
    13. Dopant activation method according to any one of claims 1 to 12, wherein the protective block (3) is deposited on the layer of semiconductor material (1 b), then the electrical doping impurities (2). ) are implanted in the layer of semiconductor material (1b) through the protective block (3) before carrying out the heat treatment.
    [0014]
    14. A method of activating dopants according to any one of claims 1 to 12, wherein the silicon-based cover layer (4) is deposited on the protection block (3), then the electrical doping impurities (2). ) are implanted in the layer of semiconductor material (1b) through the protective block (3), and through the cover layer (4) before carrying out the heat treatment.
    [0015]
    15. The method of activating dopants according to any one of claims 1 to 14, wherein the implantation step is carried out at a temperature between 15 and 700 ° C.
    [0016]
    16. A dopant activation method according to any one of claims 1 to 15, wherein the heat treatment step is carried out under an atmosphere comprising a gas selected from N2, NF3, NH3, Ar, He, or mixtures thereof. N2 / H2 or Ar / H2.
    [0017]
    17. A method of activating dopants according to any one of claims 1 to 16, wherein the heat treatment step comprises at least one annealing performed at a temperature above 1000 ° C.
    [0018]
    18. dopant activation method according to any one of claims 1 to 17, wherein the heat treatment is carried out at a pressure of between 1 and 15 kbar, preferably between 1 bar and 1 kbar, and ideally between 1 and 10 bar.
    [0019]
    19. Method for activating dopants according to any one of claims 1 to 18, wherein the thickness of the layer of semiconductor material (Ib) is between 5 nm and 10 μm, preferably between 500 nm and 1 μm. ideally equal to lpm.
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    同族专利:
    公开号 | 公开日
    US20160093510A1|2016-03-31|
    US9514962B2|2016-12-06|
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    JP2016072629A|2016-05-09|
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    法律状态:
    2015-09-30| PLFP| Fee payment|Year of fee payment: 2 |
    2016-04-01| PLSC| Publication of the preliminary search report|Effective date: 20160401 |
    2016-09-28| PLFP| Fee payment|Year of fee payment: 3 |
    2017-09-29| PLFP| Fee payment|Year of fee payment: 4 |
    2018-09-28| PLFP| Fee payment|Year of fee payment: 5 |
    2019-09-30| PLFP| Fee payment|Year of fee payment: 6 |
    2021-06-11| ST| Notification of lapse|Effective date: 20210506 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1459126A|FR3026558B1|2014-09-26|2014-09-26|METHOD FOR ACTIVATING DOPANTS IN A SEMICONDUCTOR LAYER BASED ON GAN|
    FR1459126|2014-09-26|FR1459126A| FR3026558B1|2014-09-26|2014-09-26|METHOD FOR ACTIVATING DOPANTS IN A SEMICONDUCTOR LAYER BASED ON GAN|
    EP15184347.1A| EP3001450B1|2014-09-26|2015-09-08|Method for activating p-type dopants in a gan semiconductor layer|
    US14/859,860| US9514962B2|2014-09-26|2015-09-21|Method for performing activation of dopants in a GaN-base semiconductor layer|
    JP2015187790A| JP6804185B2|2014-09-26|2015-09-25|Methods for Performing Dopant Activation in GaN-Based Semiconductor Layers|
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